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INTEGRATED CIRCUITS
DATA SHEET
UDA1342TS Audio CODEC
Product specification Supersedes data of 2000 Mar 29 File under Integrated Circuits, IC01 2000 Jul 31
Philips Semiconductors
Product specification
Audio CODEC
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.14.1 8.14.2 8.14.3 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.15.5 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock ADC analog front-end Application with 2 V (RMS) input Double differential mode Decimation filter (ADC) Digital mixer (ADC) Interpolation filter (DAC) Mute Digital mixer (DAC) Noise shaper Filter stream DAC Digital interface Sampling speed Power-on reset Control modes Static pin mode System clock setting select Digital interface format select ADC input channel select L3-bus interface Introduction Device addressing Register addressing Data write mode Data read mode I2C-bus interface Addressing Slave address Register address Write cycle Read cycle REGISTER MAPPING Reset Quick mode switch Bypass mixer DC filter DC filter ADC mode ADC polarity System clock frequency Data format 2 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 23
UDA1342TS
DAC power control Input oversampling rate DAC polarity DAC mixing position switch DAC mixer Silence detection period Multi purpose output Mode Bass boost Treble Silence detector switch Mute Quick mute mode De-emphasis ADC input amplifier gain DAC volume control DAC mixer volume control ADC mixer gain control LIMITING VALUES HANDLING QUALITY SPECIFICATION THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS TIMING APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2000 Jul 31
Philips Semiconductors
Product specification
Audio CODEC
1 FEATURES
UDA1342TS
General * 2.7 to 3.6 V power supply * 5 V tolerant digital inputs * High pin compatibility with UDA1341TS * 24 bits data path * Selectable control via L3-bus interface, I2C-bus interface or static pin control; choice of 2 device addresses in L3-bus and I2C-bus mode * Supports sample frequencies from 16 to 110 kHz * Separate power control for ADC and DAC * ADC and Programmable Gain Amplifiers (PGA) plus integrated high-pass filter to cancel DC offset * Integrated digital filter plus DAC * Digital silence detection * No analog post filtering required for DAC * Slave mode only applications * Easy application. Multiple format data interface * I2S-bus, MSB-justified and LSB-justified format compatible * 1fs to 4fs input and 1fs output format data rate. DAC digital sound processing * Separate digital logarithmic volume control for left and right channels in L3-bus mode or I2C-bus mode * Digital tone control, bass boost and treble in L3-bus mode or I2C-bus mode * Digital de-emphasis for sample frequencies of 32, 44.1, 48 and 96 kHz in L3-bus mode or I2C-bus mode * Soft or quick mute in L3-bus mode or I2C-bus mode * Output signal polarity control in L3-bus mode or I2C-bus mode * Digital mixer for ADC output signal and digital serial input signal. Advanced audio configuration * 4 channel (2 x stereo) single-ended inputs with programmable gain amplifiers and 2 channel (1 x stereo) single-ended outputs configuration * Output signal polarity control in L3-bus mode or I2C-bus mode * High linearity, wide dynamic range, low distortion * Double differential input configuration for enhanced ADC sound quality. 2 APPLICATIONS
* Eminently suitable for MiniDisc (MD) home and portable applications. 3 GENERAL DESCRIPTION
The UDA1342TS is a single-chip 4 channel analog-to-digital converter and 2 channel digital-to-analog converter with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. The UDA1342TS supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. The device also supports a combination of the MSB-justified output format and the LSB-justified input format. The UDA1342TS has special sound processing features in the playback mode such as de-emphasis, volume, mute, bass boost and treble, which can be controlled by the microcontroller via the L3-bus or I2C-bus interface.
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Philips Semiconductors
Product specification
Audio CODEC
4 QUICK REFERENCE DATA SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current 1 ADC + 1 PGA enabled 2 ADCs + 2 PGAs enabled all ADCs + all PGAs power-down IDDA(DAC) IDDD DAC analog supply current digital supply current operating DAC power-down operating ADC power-down DAC power-down Tamb Vi(rms) (THD+N)/S48 ambient temperature Analog-to-digital convertor input voltage (RMS value) at 0 dB (FS) digital output - - - - - - - - - - - 0.9 2.7 2.7 2.7 - - - - - - - - -40 PARAMETER CONDITIONS MIN.
UDA1342TS
TYP.
MAX.
UNIT
3.0 3.0 3.0 10.0 20.0 200 6.0 250 9.0 4.5 5.5 -
3.6 3.6 3.6 - - - - - - - - +85 - - - - - - - - - - -
V V V mA mA A mA A mA mA mA C V dB dB dB dB dB dB dB dB dB dB
total harmonic distortion-plus-noise normal mode to signal ratio at fs = 48 kHz at -1 dB at -60 dB; A-weighted double differential at -1 dB at -60 dB; A-weighted
-90 -40 -93 -41 -84 -39 100 101 99 100
(THD+N)/S96
total harmonic distortion-plus-noise normal mode to signal ratio at fs = 96 kHz at -1 dB at -60 dB; A-weighted signal-to-noise ratio at fs = 48 kHz normal mode; Vi = 0 V; A-weighted double differential mode; Vi = 0 V; A-weighted
S/N48
S/N96 cs
signal-to-noise ratio at fs = 96 kHz channel separation
normal mode; Vi = 0 V; A-weighted
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - -
TYP.
MAX. - - - - - - - -
UNIT
Digital-to-analog convertor Vo(rms) (THD+N)/S48 (THD+N)/S96 S/N48 S/N96 cs Note 1. The output voltage of the DAC is proportionally to the DAC power supply voltage. 5 ORDERING INFORMATION TYPE NUMBER UDA1342TS PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1 output voltage (RMS value) at 0 dB (FS) digital input; note 1 0.9 -90 -40 -83 -39 100 99 100 V dB dB dB dB dB dB dB
total harmonic distortion-plus-noise at 0 dB to signal ratio at fs = 48 kHz at -60 dB; A-weighted total harmonic distortion-plus-noise at 0 dB to signal ratio at fs = 96 kHz at -60 dB; A-weighted signal-to-noise ratio at fs = 48 kHz signal-to-noise ratio at fs = 96 kHz channel separation code = 0; A-weighted code = 0; A-weighted
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Philips Semiconductors
Product specification
Audio CODEC
6 BLOCK DIAGRAM
UDA1342TS
handbook, full pagewidth
VDDA(ADC) 3 6
VSSA(ADC) 1
VDDD 10
VSSD 11
VADCP 7
VADCN 5 8
VINL2
VINR2
PGA ADC VINL1 2 PGA ADC ADC
PGA 4 PGA ADC 9 VINR1 IPSEL
UDA1342TS
DECIMATION FILTER DIGITAL MIXER (ADC)
22 23
STATUS QMUTE
DC-CANCELLATION FILTER 18 16 17 19 DIGITAL INTERFACE L3-BUS/ I2C-BUS INTERFACE 13 14 15
DATAO BCK WS DATAI
L3MODE L3CLOCK L3DATA
DIGITAL MIXER (DAC) DSP FEATURES
21 12
STATIC SYSCLK
INTERPOLATION FILTER 20
NOISE SHAPER
TEST1
DAC 26
DAC 24
VOUTL
VOUTR
25 VDDA(DAC)
28 Vref
27 VSSA(DAC)
MGT016
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Audio CODEC
7 PINNING SYMBOL VSSA(ADC) VINL1 VDDA(ADC) VINR1 VADCN VINL2 VADCP VINR2 IPSEL VDDD VSSD SYSCLK L3MODE L3CLOCK L3DATA BCK WS DATAO DATAI TEST1 STATIC STATUS QMUTE VOUTR VDDA(DAC) VOUTL VSSA(DAC) Vref PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 analog ground pad analog input pad analog supply pad analog input pad analog pad analog input pad analog pad analog input pad 5 V tolerant digital input pad digital supply pad digital ground pad 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant open drain input/output 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant 2 mA slew rate controlled digital output 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant digital input pad 5 V tolerant 2 mA slew rate controlled digital output 5 V tolerant digital input pad analog output pad analog supply pad analog output pad analog ground pad analog pad TYPE ADC input left 1
UDA1342TS
DESCRIPTION ADC analog ground ADC analog supply voltage ADC input right 1 ADC reference voltage N ADC input left 2 ADC reference voltage P ADC input right 2 channel select input: input left 1 and right 1 or input left 2 and right 2 digital supply voltage digital ground system clock input: 256fs, 384fs, 512fs or 768fs L3-bus mode input or mode selection input L3-bus/I2C-bus clock input or clock selection input L3-bus/I2C-bus data input/output or format selection input bit clock input word select input data output data input test control input; to be connected to ground mode selection input: static pin control or L3-bus/I2C-bus control general purpose output quick mute input DAC output right DAC analog supply voltage DAC output left DAC analog ground reference voltage for ADC and DAC
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Philips Semiconductors
Product specification
Audio CODEC
8.2
handbook, halfpage
UDA1342TS
ADC analog front-end
VSSA(ADC) 1 VINL1 2
28 Vref 27 VSSA(DAC) 26 VOUTL 25 VDDA(DAC) 24 VOUTR 23 QMUTE 22 STATUS
The analog front-end of the UDA1342TS consists of two stereo ADCs with a programmable gain stage (gain from 0 to 24 dB with 3 dB steps) which can be controlled via the L3-bus/I2C-bus interface. 8.2.1 APPLICATION WITH 2 V (RMS) INPUT
VDDA(ADC) 3 VINR1 4 VADCN 5 VINL2 6 VADCP 7
UDA1342TS
VINR2 8 IPSEL 9 VDDD 10 VSSD 11 SYSCLK 12 L3MODE 13 L3CLOCK 14
MGT017
21 STATIC 20 TEST1 19 DATAI 18 DATAO 17 WS 16 BCK
In applications in which a 2 V (RMS) input signal is used, a 15 k resistor must be used in series with the input of the ADC (see Fig.3). This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the gain switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1. Table 1 Application modes using input gain stage PGA GAIN 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS)
15 L3DATA
RESISTOR (15 k) Present Present Absent Absent
Fig.2 Pin configuration.
8 8.1
FUNCTIONAL DESCRIPTION System clock
The UDA1342TS operates in slave mode only, this means that in all applications the system must provide the system clock. The system clock frequency is selectable and depends on the mode of operation: * L3-bus/I2C-bus mode: 256fs, 384fs, 512fs or 768fs * Static pin mode: 256fs or 384fs. The system clock must be locked in frequency to the digital interface signals. Remarks: * The bit clock frequency fBCK can be up to 128fs, or in other words the bit clock frequency is 128 times the word select frequency fWS or less: fBCK 128fWS * The WS edge MUST fall on the negative edge of the BCK signal at all times for proper operation of the digital interface * The UDA1342TS operates with sample frequencies from 16 to 110 kHz, however for a system clock of 768fs the sampling frequency must be limited to 55 kHz. 2000 Jul 31 8 Fig.3 Schematic of ADC front-end.
handbook, halfpage
input signal 2 V (RMS)
15 k
VINL1, VINR1, VINL2, VINR2
2, 4, 6, 8 10 k Vref
gain = 0 dB 10 k
UDA1342TS
MGT018
Philips Semiconductors
Product specification
Audio CODEC
8.2.2 DOUBLE DIFFERENTIAL MODE 8.6 Mute
UDA1342TS
Since the UDA1342TS is equipped with two stereo ADCs, these two pairs of stereo ADCs can be used to convert a single stereo signal to a signal with a higher performance by using the ADCs in the double differential mode. This mode and the input signals, being channel 1 or 2 as input to the double differential configuration, can be selected via the L3-bus/I2C-bus interface. 8.3 Decimation filter (ADC)
Muting the DAC will result in a cosine roll-off soft mute, using 32 x 32 = 1024 samples in the normal mode: this results in 24 ms at fs = 44.1 kHz. The cosine roll-off curve is illustrated in Fig.4. This cosine roll-off functions are implemented in the DAC data path before the digital mixer and before the master mute (see Fig.5). In the L3-bus and I2C-bus mode, the setting of the master mute can be overruled always by pin QMUTE. This quick mute uses the same cosine roll-off, but now for only 32 samples: this is 750 s at fs = 44.1 kHz.
The decimation from 64fs to 1fs is performed in two stages. sin x 4 The first stage realizes a ---------- characteristic with a x - decimation factor of 8. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 2. Table 2 Decimation filter characteristics CONDITION 0 to 0.45fs 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.01 -0.2 -70 >135
handbook, halfpage
1
MGU119
mute factor 0.8
ITEM Pass-band ripple Pass-band droop Stop band Dynamic range 8.4
0.6
0.4
Digital mixer (ADC)
0.2
The two stereo ADC outputs are mixed with gain coefficients from +24 to -63.5 dB to be set via the microcontroller interface. In front of the mixer there is a DC filter. In order to prevent clipping, it is needed to filter out the DC component before mixing or amplifying the signals. The mixing function can be enabled via the microcontroller interface. 8.5 Interpolation filter (DAC) 8.7
0 0 5 10 15 20 t (ms) 25
Fig.4 Mute as a function of raised cosine roll-off.
Digital mixer (DAC)
The ADC output signal and the digital interface input signal can be mixed without an external DSP (see Fig.5). This mixer can be controlled via the microcontroller interface. In order to prevent clipping when mixing two 0 dB signals, the signals are attenuated digitally by -6 dB before mixing. After mixing the signal is gained by 6 dB after the master volume. This way clipping at the digital mixer is prevented. After the 6 dB gain, the signals can clip again, but this clipping can be removed by decreasing the master volume.
The digital interpolation filter interpolates from 1fs to 64fs by means of a cascade of FIR filters. The filter characteristics are shown in Table 3. Table 3 Interpolation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.025 -60 >135
ITEM Pass-band ripple Stop band Dynamic range
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
handbook, full pagewidth
to digital interface output VOLUME AND MUTE master
from decimation filter from digital interface input
DE-EMPHASIS
VOLUME AND MUTE
+
BASS BOOST AND TREBLE
+
VOLUME AND MUTE
MGT019
to interpolation filter
Fig.5 Digital mixer (DAC).
8.8
Noise shaper
8.10
Digital interface
The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). 8.9 Filter stream DAC
The UDA1342TS supports the following data input/output formats for the various modes (see Fig.6). L3-bus and I2C-bus mode: * I2S-bus format with data word length of up to 24 bits * MSB-justified serial format with data word length of up to 24 bits * LSB-justified serial format with data word lengths of 16, 20 or 24 bits * MSB-justified data output and LSB-justified 16, 20 and 24 bits data input. Static pin mode: * I2S-bus format with data word length of up to 24 bits * MSB-justified data output and LSB-justified 16, 20 and 24 bits data input.
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is proportionally to the power supply voltage.
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WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT DATA MSB B2 MSB B2 I2S-BUS FORMAT WS 1 BCK 2 LEFT 3 >=8 1 2 RIGHT 3 >=8 DATA MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT WS LEFT 16 BCK 15 2 1
Philips Semiconductors
handbook, full pagewidth
Audio CODEC
>=8
MSB
LSB
MSB
B2
RIGHT 16 15 2 1
11
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT 20 19 18 17 16 15 2 1
UDA1342TS
Product specification
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB-JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGT020
Fig.6 Serial interface input/output formats.
Philips Semiconductors
Product specification
Audio CODEC
8.11 Sampling speed
UDA1342TS
Important: in the double speed mode an input signal of 0 dB is allowed, but in the quad speed mode the input signal must be limited to -6 dB to prevent the system from clipping.
The UDA1342TS operates with sample frequencies from 16 to 110 kHz. This range holds for the CODEC as a whole. The DAC part can be configured in the L3-bus and I2C-bus mode to accept 2 times and even 4 times the data speed (e.g. fs is 96 or 192 kHz), but in these modes not all of the features can be used. Some examples of the input oversampling rate settings are shown in Table 4. Table 4 Examples of the input oversampling rate settings SYSTEM CLOCK FREQUENCY SETTING 256fs
SYSTEM CLOCK 12.288 MHz (256 x 48 kHz)
SAMPLING FREQUENCY (kHz) 48 96 192
INPUT OVERSAMPLING RATE single speed double speed quad speed single speed single speed double speed single speed single speed double speed all
FEATURES SUPPORTED
only master volume and mute no features all all only master volume and mute all all only master volume and mute
22.5792 MHz (512 x 44.1 kHz)
512fs 256fs
44.1 88.2 176.4 44.1 88.2 176.4
33.8688 MHz (768 x 44.1 kHz)
768fs 384fs
8.12
Power-on reset
The UDA1342TS has an internal Power-on reset circuit (see Fig.7) which resets the test control block. All the digital sound processing features and the system controlling features are set to their default setting in the L3-bus and I2C-bus mode. The reset time (see Fig.8) is determined by an external capacitor which is connected between pin Vref and ground. The reset time should be at least 1 s for Vref < 1.25 V. When VDDA(DAC) is switched off, the device will be reset again for Vref < 0.75 V. During the reset time the system clock should be running.
handbook, halfpage VDDA(DAC) 25
3.0 V
8 k Vref 28 C1 > 10 F 8 k RESET CIRCUIT
UDA1342TS
MGU001
Fig.7 Power-on reset circuit.
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
handbook, halfpage
3.0 VDDD (V) 1.5
0 t 3.0 VDDA(DAC) (V) 1.5
0 t 3.0 Vref (V) 1.5
1.25 0.75
0 >1 s t
MGU002
Fig.8 Power-on reset timing.
8.13
Control modes
Table 6
Pin function in the selected mode FUNCTION
The control mode can be set with pin STATIC and pin L3MODE: * Static pin mode * I2C-bus mode * L3-bus mode. Table 5 Mode selection PIN L3MODE - LOW HIGH SELECTION L3-bus mode I2C-bus mode static pin mode
PIN NAME L3CLOCK L3MODE L3DATA QMUTE IPSEL
L3-BUS MODE L3CLOCK L3MODE L3DATA QMUTE A0
I2C-BUS MODE SCL LOW level SDA QMUTE A0
STATIC PIN MODE clock select HIGH level format select format select channel select
PIN STATIC LOW HIGH HIGH
All features in the L3-bus and I2C-bus mode are explained in Sections 8.15 and 8.16.
The pin functions in the various modes are summarized in Table 6.
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Philips Semiconductors
Product specification
Audio CODEC
8.14 Static pin mode 8.15 L3-bus interface
UDA1342TS
The controllable features in the static pin mode are: * System clock frequency * Data input and output format select * ADC input channel select. 8.14.1 SYSTEM CLOCK SETTING SELECT
All digital processing features and system controlling features of the UD1342TS can be controlled by a microcontroller via the L3-bus interface. The controllable features are: * Reset * System clock frequency * Data input and output format * Multi purpose output * ADC features - Operation mode control - Polarity control - Input amplifier gain control - Mixer control - DC filtering. * DAC features - Power control - Polarity control - Input data oversampling rate - Mixer position selection - Mixer control - Silence detector - De-emphasis - Volume - Flat/min./max. switch - Bass boost - Treble - Mute - Quick mute mode. 8.15.1 INTRODUCTION
In the static pin mode pin L3CLOCK is used to select the system clock setting. Table 7 System clock setting SYSTEM CLOCK SETTING 256fs 384fs
PIN L3CLOCK 0 1 8.14.2
DIGITAL INTERFACE FORMAT SELECT
In the static pin mode the digital interface audio formats can be selected via pins L3DATA and QMUTE. The following interface formats can be selected (see Table 8): * I2S-bus format with data word length of up to 24 bits * MSB-justified output format and LSB-justified input format with data word length of 16, 20 or 24 bits. Table 8 PIN L3DATA 0 0 1 1 Data format select in static pin mode PIN QMUTE 0 1 0 1 INPUT/OUTPUT FORMAT I2S LSB-justified 16 bits input and MSB-justified output LSB-justified 20 bits input and MSB-justified output LSB-justified 24 bits input and MSB-justified output
8.14.3
ADC INPUT CHANNEL SELECT
In the static pin mode pin IPSEL selects the ADC input channel. Table 9 PIN IPSEL 0 1 ADC input channel select CHANNEL SELECT input channel 1 (pins VINL1 and VINR1) input channel 2 (pins VINL2 and VINR2)
The exchange of data and control information between the microcontroller and the UDA1342TS is accomplished through a serial hardware interface comprising the following pins: * L3DATA: microcontroller interface data line * L3MODE: microcontroller interface mode line * L3CLOCK: microcontroller interface clock line. The UDA1342TS acts as a slave receiver or a slave transmitter. Therefore L3CLOCK and L3MODE lines transfer only input data and the L3DATA line transfers bidirectional data.
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Philips Semiconductors
Product specification
Audio CODEC
Information transfer via the microcontroller bus is organized LSB first and in accordance with the so called `L3' format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Important: * When the device is powered-up, at least one L3CLOCK pulse must be sent to the L3-bus interface to wake-up the interface prior to sending information to the device. This is only needed once after the device is powered-up. * Inside the microcontroller there is a hand-shake mechanism which handles proper data transfer from the microcontroller clock to destination clock domains. This means that when data is sent to the microcontroller interface, the system clock must be running. * The L3-bus interface is designed in such a way that data is clocked into the device (write mode) on the positive clock edge, while the device starts the output data (read mode) on the negative clock edge. The microcontroller must read the data from the device on the positive clock edge to ensure the data is always stable. 8.15.2 DEVICE ADDRESSING Table 11 Selection of data transfer DOM
UDA1342TS
TRANSFER BIT 0 0 1 0 1 8.15.3 BIT 1 0 0 1 1 not used not used data write or prepare read data read
REGISTER ADDRESSING
After sending the device address, including the flags (DOM bits) whether the information is read or written, the data transfer mode is entered and one byte is sent with the destination register address (see Table 12) using 7 bits, and one bit which signals whether information will be read or written. The fundamental timing for the data transfer mode is given in Fig.14. Table 12 L3-bus register address LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB R/W A6 A5 A4 A3 A2 A1 A0
The device address mode is used to select a device for subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits. The fundamental timing in the address mode is shown in Fig.13. The device address consists of one byte, which is split up in two parts (see Table 10): * Bits 0 and 1 are called Data Operation Mode (DOM) bits and represent the type of data transfer * Bits 2 to 7 represent a 6-bit device address. Table 10 L3-bus interface slave address DOM DEVICE ADDRESS
Basically there are 3 cases for register addressing: 1. Register addressing for L3-bus write: the first bit is at logic 0 indicating a write action to the destination register, and is followed by 7 bits indicating the register address. 2. Prepare read addressing: the first bit of the byte is at logic 1, signalling data will be read from the register indicated. 3. Read action itself: in this case the device returns a register address prior to sending data from that register. When the first bit of the byte is at logic 0, the register address was valid and if the first bit is at logic 1 the register address was invalid. Important: 1. Each time a new destination address needs to be written, the device address must be sent again. 2. When addressing the device for the first time after power-up of the device, at least one L3CLOCK cycle must be given to enable the L3-bus interface.
LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB R/W 1 IPSEL 0 1 0 0 0
The UDA1342TS can be set to different addresses (00 1000 or 10 1000) by setting pin IPSEL to HIGH or LOW level. In the event that the device receives a different address, it will deselect its microcontroller interface logic. Basically, 2 types of data transfer can be defined: data transfer to the device and data transfer from the device (see Table 11).
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Philips Semiconductors
Product specification
Audio CODEC
8.15.4 DATA WRITE MODE
UDA1342TS
The data read mode is explained below: 1. One byte with the device address, being `01X0 1000' where `X' stands for the IPSEL value, including `01' for signalling write to the device. 2. One byte is sent with the register address which needs to be read. This byte starts with a logic 1, which indicates that there will be a read action from the register. 3. One byte with the device address including `11' is sent to the device. The `11' indicates that the device must write data to the microcontroller. 4. The device now writes the requested register address on the L3-bus, indicating whether the requested register was valid (logic 0) or invalid (logic 1). 5. The device writes data from the requested register to the L3-bus with the MSD byte 1 first, followed by the LSD byte 2.
The data write format is given in Table 13 and illustrated in Fig.9. When writing data to a device four bytes must be sent: 1. One byte with the device address, being `01X0 1000' where `X' stands for the IPSEL value, including `01' for signalling write to the device. 2. One byte starting with a logic 0 for signalling write followed by 7 bits indicating the register address. 3. One byte which is the Most Significant Data (MSD) byte 1. 4. One byte which is the Least Significant Data (LSD) byte 2. 8.15.5 DATA READ MODE
The data write format is given in Table 14 and illustrated in Fig.10. When reading from the device, a prepare read must first be done. After the prepare read, the device address is sent again. The device then returns with the register address, indicating whether the address was valid or not, and the data of the register. Table 13 L3-bus format for data write
FIRST IN TIME L3MODE Address Data transfer 1 Data transfer 2 Data transfer 3 DATA TYPE BIT 0 device address register address MSD byte 1 LSD byte 2 0 0 D15 D7 BIT 1 1 A6 D14 D6 BIT 2 IPSEL A5 D13 D5 BIT 3 0 A4 D12 D4 BIT 4 1 A3 D11 D3 BIT 5 0 A2 D10 D2
LAST IN TIME BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0
Table 14 L3-bus format for prepare read and read data FIRST IN TIME L3MODE Prepare read Address Data transfer 1 Read data Address Data transfer 1 Data transfer 2 Data transfer 3 device address register address MSD byte 1 LSD byte 2 1 0/1 D15 D7 1 A6 D14 D6 IPSEL A5 D13 D5 0 A4 D12 D4 1 A3 D11 D3 0 A2 D10 D2 0 A1 D9 D1 0 A0 D8 D0 device address register address 0 1 1 A6 IPSEL A5 0 A4 1 A3 0 A2 0 A1 0 A0 DATA TYPE BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 LAST IN TIME
2000 Jul 31
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L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 0
MGS753
Philips Semiconductors
Audio CODEC
register address
data byte 1
data byte 2
DOM bits
write
Fig.9 Data write mode for L3-bus version 2. 17
L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2
UDA1342TS
Product specification
valid/non-valid send by the device
MGS754
Fig.10 Data read mode for L3-bus version 2.
Philips Semiconductors
Product specification
Audio CODEC
8.16 I2C-bus interface 8.16.3 REGISTER ADDRESS
UDA1342TS
Besides the L3-bus mode the UDA1342TS supports the I2C-bus mode; all the features can be controlled by the microcontroller with the same register addresses as used in the L3-bus mode. The exchange of data and control information between the microcontroller and the UDA1342TS in the I2C-bus mode is accomplished through a serial hardware interface comprising the following pins and signals: * L3CLOCK: Serial Clock Line (SCL) * L3DATA: Serial Data line (SDA). The clock and data timing of the I2C-bus transfer is shown in Fig.15. 8.16.1 ADDRESSING
The UDA1342TS register address format is given in Table 16. Table 16 I2C-bus register address format MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB 0 A6 A5 A4 A3 A2 A1 A0
The register mapping of the I2C-bus and L3-bus interfaces is the same (see Section 9).
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure (S). 8.16.2 SLAVE ADDRESS
The UDA1342TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is an input or output signal (bidirectional line). The UDA1342TS slave address format is shown in Table 15. Table 15 I2C-bus slave address format MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB 0 0 1 1 0 1 IPSEL R/W
The slave address bit IPSEL corresponds to the hardware address pin IPSEL which allows selecting the slave address.
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Audio CODEC
The write cycle is used to write data from the microcontroller to the internal registers. The I2C-bus format for a write cycle is shown in Table 17. The device and register addresses are one byte each, data is always two bytes (2-bytes data). The format of the write cycle is as follows: 1. The microcontroller starts with a START condition S. 2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W = 0). 3. This is followed by an acknowledge (A) from the UDA1342TS. 4. The microcontroller then writes the register address (8 bits) where writing of the register content of the UDA1342TS must start. 5. The UDA1342TS acknowledges this register address. 6. The microcontroller sends 2-bytes data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where each byte is acknowledged by the UDA1342TS. 7. After the last acknowledge the UDA1342TS frees the I2C-bus and the microcontroller can generate a STOP condition (P). Table 17 Master transmitter writes to UDA1342TS registers ACKNOWLEDGE FROM UDA1342TS DEVICE ADDRESS 0011 01X 8 bits R/W 0 A REGISTER ADDRESS 0XXX XXXX 8 bits A MSD1 8 bits A LSD1 8 bits A MSD2 8 bits DATA(1) A LSD2 8 bits A MSDn 8 bits A LSDn 8 bits A P
UDA1342TS
Product specification
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Audio CODEC
The read cycle is used to read data from the internal registers of the UDA1342TS to the microcontroller. The I2C-bus format for a read cycle is shown in Table 18. The format of the read cycle is as follows: 1. The microcontroller starts with a START condition S. 2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W = 0). 3. This is followed by an acknowledge (A) from the UDA1342TS. 4. The microcontroller then writes the register address where reading of the register content of the UDA1342TS must start. 5. The UDA1342TS acknowledges this register address. 6. Then the microcontroller generates a repeated START (Sr). 7. Again the device address 0011 01X is given, but this time followed by a read command (bit R/W = 1). 8. The UDA1342TS sends the two-byte data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where each byte is acknowledged by the microcontroller (master). 9. The microcontroller stops this cycle by generating a negative acknowledge (NA). 10. The UDA1342TS then frees the I2C-bus and the microcontroller can generate a STOP condition (P). Table 18 Master transmitter reads from UDA1342TS registers ACKNOWLEDGE FROM UDA1342TS DEVICE R/W ADDRESS S 0011 01X 8 bits Note 1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted. 0 REGISTER ADDRESS A 0XXX XXXX A Sr 8 bits DEVICE R/W ADDRESS 0011 01X 8 bits 1 A MSD1 8 bits A LSD1 8 bits A MSD2 8 bits ACKNOWLEDGE FROM MASTER DATA(1) A LSD2 8 bits A MSDn 8 bits A LSDn 8 bits NA P
UDA1342TS
Product specification
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Audio CODEC
The addresses of the control registers with default values at Power-on reset are shown in Table 19. Functions of the registers are shown in Tables 20 to 45. Table 19 Register map ADDRESS 00H 01H FUNCTION system sub system D15 RST - - - 02H to 0FH reserved 10H 11H 12H DAC features DAC master volume DAC mixer volume - M1 0 VL7 0 VB7 0 13H to 1FH reserved 20H 21H ADC input and mixer gain channel 1 ADC input and mixer gain channel 2 - 0 0 0 0 - 0 - D14 QS 0 - - - M0 0 VL6 0 VB6 0 - 0 0 0 0 - 0 - D13 MDC 0 - - - BB3 0 VL5 0 VB5 0 - 0 0 0 0 - 0 - D12 DC 1 - - - BB2 0 VL4 0 VB4 0 - 0 0 0 0 - 0 - D11 1 - - - BB1 0 VL3 0 VB3 0 - IA3 0 IB3 0 - 0 - D10 0 - - - BB0 0 VL2 0 VB2 0 - IA2 0 IB2 0 - 0 - D9 1 - - - TR1 0 VL1 0 VB1 0 - IA1 0 IB1 0 - 0 - D8 PAD 0 - - - TR0 0 VL0 0 VB0 0 - IA0 0 IB0 0 - 0 - D7 0 0 0 - 0 VR7 0 VA7 0 - 0 0 - 0 - D6 SC1 0 0 - 0 VR6 0 VA6 0 - 0 0 - 0 - D5 SC0 0 0 - 0 VR5 0 VA5 0 - 0 0 - 0 - D4 IF2 0 MIX 0 - MT 0 VR4 0 VA4 0 - 0 0 - 0 - D3 IF1 0 SD1 0 - QM 0 VR3 0 VA3 0 - 0 0 - 0 - D2 IF0 0 0 - DE2 0 VR2 0 VA2 0 - 0 0 - 0 - D1 DP 1 0 - 0 0 VA1 0 - 0 0 - 0 - D0 PDA 0 0 - 0 0 VA0 0 - 0 0 - 0 -
AM2 AM1 AM0
OS1 OS0 MPS
SD0 MP1 MP0
SDS MTB MTA
DE1 DE0 VR1 VR0
MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
22H to 2FH reserved 30H evaluation 31H to FFH reserved
UDA1342TS
Product specification
Philips Semiconductors
Product specification
Audio CODEC
9.1 Reset I2C-bus 9.5 ADC mode
UDA1342TS
registers A 1-bit value to initialize the L3-bus and except the system register (00H) with default settings by setting bit RST = 1. Table 20 Reset bit RST 0 1 9.2 no reset reset registers to default FUNCTION
A 3-bit value to select the mode of the ADC. Table 24 ADC mode AM2 AM1 AM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FUNCTION ADC power-off input 1 select (input 2 off) input 2 select (input 1 off) not used channel swap and signal inversion input 1 select (double differential mode) input 2 select (double differential mode) mixing mode
Quick mode switch
A 1-bit value to enable the quick mode change of the ADC. The soft mode change works only between modes if bit AM2 = 1. Table 21 Quick mode switch QS 0 1 9.3 FUNCTION soft mode change quick mode change
9.6
ADC polarity
A 1-bit value to control the ADC polarity. Table 25 Polarity control of the ADC
Bypass mixer DC filter PAD 0 1 9.7 FUNCTION enable mixer DC filtering disable mixer DC filtering inverting FUNCTION non-inverting
A 1-bit value to disable the DC filter of the ADC mixer. This DC filter is in front of the mixer to prevent clipping inside the mixer due to DC signals. Table 22 Mixer DC filtering MDC 0 1 9.4 DC filter
System clock frequency
A 2-bit value to select the external clock frequency. Table 26 System clock frequency settings SC1 0 0 1 1 SC0 0 1 0 1 256fs 384fs 512fs 768fs FUNCTION
A 1-bit value to enable the DC filter of the ADC output. This DC filter is inside the decimation filter. Table 23 DC-filtering DC 0 1 FUNCTION disable output DC filtering enable output DC filtering
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Philips Semiconductors
Product specification
Audio CODEC
9.8 Data format 9.11 DAC polarity
UDA1342TS
A 3-bit value to select the data format. Table 27 Data format selection IF2 0 0 0 0 1 1 1 1 IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified16 bits LSB-justified 20 bits LSB-justified 24 bits MSB-justified LSB-justified 16 bits input and MSB-justified output LSB-justified 20 bits input and MSB-justified output LSB-justified 24 bits input and MSB-justified output FUNCTION
A 1-bit value to control the DAC polarity. Table 29 Polarity control of DAC PDA 0 1 9.12 non-inverting inverting FUNCTION
DAC mixing position switch
A 1-bit value to select the mixing position of the ADC signal in the DAC. Table 30 DAC mixing position switch MPS 0 1 9.13 FUNCTION before sound features after sound features
9.9
DAC power control
DAC mixer
A 1-bit value to disable the DAC to reduce power consumption. The DAC power-off is not recommended when the DAC outputs are DC loaded. Table 28 DAC power control DP 0 1 9.10 FUNCTION DAC power-off DAC power-on
A 1-bit value to enable the digital mixer of the DAC. Table 31 DAC mixer MIX 0 1 disable mixer enable mixer FUNCTION
Input oversampling rate
A 2-bit value to select the oversampling rate of the input signal (see Table 32). In the quad speed input rate, care must be taken that the input signal is smaller than -5.67 dB (FS). Table 32 Input oversampling rate OS1 0 0 1 1 OS0 0 1 0 1 MODE single speed double speed quad speed reserved SAMPLING FREQUENCY 16 to 110 kHz 32 to 220 kHz 64 to 440 kHz - ADC supported not supported not supported - DAC FEATURES all digital filters and all features, including mixing are available first digital filter is bypassed, only master volume and master mute features are available no mixing nor any sound feature is supported -
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Philips Semiconductors
Product specification
Audio CODEC
9.14 Silence detection period Table 36 Bass boost settings
UDA1342TS
A 2-bit value to define the silence period for the silence detector. Table 33 Silence detection period SD1 0 0 1 1 9.15 SD0 0 1 0 1 FUNCTION 3200 samples 4800 samples 9600 samples 19200 samples
BASS BOOST (dB) BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9.18 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Treble BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 FLAT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 MAX. 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
Multi purpose output
A 2-bit value to select the output signal on pin STATUS. Table 34 Multi purpose output selection MP1 0 0 1 1 9.16 MP0 0 1 0 1 Mode no output overflow (ADC) detection reserved digital silence detection FUNCTION
A 2-bit value to program the mode of the sound processing filters of bass boost and treble. Table 35 Flat/min./max. switch position M1 0 0 1 1 9.17 M0 0 1 0 1 flat min. min. max. FUNCTION
A 2-bit value to program the treble setting. The used set depends on the setting of bits M1 and M0. At fs = 44.1 kHz the -3 dB point for minimum setting is 3.0 kHz and the -3 dB point for maximum setting is 1.5 kHz. The default value is 00. Table 37 Treble settings TREBLE (dB) TR1 0 0 1 1 TR0 FLAT 0 1 0 1 0 0 0 0 MIN. 0 2 4 6 MAX. 0 2 4 6
Bass boost
A 4-bit value to program the bass boost settings. The used set depends on the setting of bits M1 and M0. At fs = 44.1 kHz the -3 dB point for minimum setting is 250 Hz and the -3 dB point for maximum setting is 300 Hz. The default value is 0000.
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Philips Semiconductors
Product specification
Audio CODEC
9.19 Silence detector switch 9.23 ADC input amplifier gain
UDA1342TS
A 1-bit value to enable the silence detector. Table 38 Silence detector switch SDS 0 1 9.20 Mute FUNCTION disable silence detector enable silence detector
Two 4-bit values to program the gain of the input amplifiers. Bits IA applies for input amplifier A and bits IB to input amplifier B. Table 42 ADC input amplifier gain settings IA3 IB3 0 0 0 0 0 0 0 0 1 IA2 IB2 0 0 0 0 1 1 1 1 0 IA1 IB1 0 0 1 1 0 0 1 1 0 IA0 IB0 0 1 0 1 0 1 0 1 0 AMPLIFIER GAIN (dB) 0 3 6 9 12 15 18 21 24
Three 1-bit values to enable the digital mute. Bit MT is the master mute, using bit MTA the signal from the digital interface can be soft muted when the DAC mixer is enabled and using bit MTB the signal from ADC can be soft muted. Table 39 Mute MT MTA MTB 0 1 9.21 no muting muting FUNCTION
Quick mute mode
A 1-bit value to enable the quick mute function of the master mute. Table 40 Quick mute mode settings QM 0 1 9.22 FUNCTION soft mute mode quick mute mode
De-emphasis
A 3-bit value to enable the digital de-emphasis filter. Table 41 De-emphasis settings DE2 0 0 0 0 1 DE1 0 0 1 1 0 DE0 0 1 0 1 0 FUNCTION no de-emphasis de-emphasis at fs = 32 kHz de-emphasis at fs = 44.1 kHz de-emphasis at fs = 48 kHz de-emphasis at fs = 96 kHz
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Philips Semiconductors
Product specification
Audio CODEC
9.24 DAC volume control
UDA1342TS
Four 8-bit values to program the volume attenuations. The range is from 0 to -66 dB and - dB in steps of 0.25 dB. Bits VL and VR are master volumes for the left and right channels. Table 43 DAC volume settings VL7 VR7 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 9.25 VL6 VR6 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 VL5 VR5 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 1 : 1 VL4 VR4 0 0 0 0 0 : 0 0 0 0 0 0 1 1 1 1 0 : 1 VL3 VR3 0 0 0 0 0 : 0 0 0 0 1 1 0 0 1 1 0 : 1 VL2 VR2 0 0 0 0 1 : 1 1 1 1 0 1 0 1 0 1 0 : 1 VL1 VR1 0 0 1 1 0 : 0 0 1 1 0 0 0 0 0 0 0 : 1 VL0 VR0 0 1 0 1 0 : 0 1 0 1 0 0 0 0 0 0 0 : 1 VOLUME (dB) 0 -0.25 -0.50 -0.75 -1.00 : -49.0 -49.25 -49.5 -49.75 -50.0 -52.0 -54.0 -57.0 -60.0 -66.0 - : -
DAC mixer volume control
Four 8-bit values to program the volume attenuations. The range is from 0 to -60 dB and - dB in steps of 0.25 dB. When the DAC mixer is enabled, the signal from the digital interface can be controlled by bits VA and the signal from the ADC can be controlled by bits VB. Table 44 DAC volume settings VA7 VB7 0 0 0 0 0 : 1 1 2000 Jul 31 VA6 VB6 0 0 0 0 0 : 0 0 VA5 VB5 0 0 0 0 0 : 1 1 VA4 VB4 0 0 0 0 0 : 0 0 VA3 VB3 0 0 0 0 0 : 1 1 VA2 VB2 0 0 0 0 1 : 1 1 26 VA1 VB1 0 0 1 1 0 : 0 0 VA0 VB0 0 1 0 1 0 : 0 1 VOLUME (dB) 0 -0.25 -0.50 -0.75 -1.00 : -43.0 -43.25
Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
VA7 VB7 1 1 1 1 1 1 1 1 1 : 1 9.26
VA6 VB6 0 0 0 0 0 0 1 1 1 : 1
VA5 VB5 1 1 1 1 1 1 0 0 0 : 1
VA4 VB4 0 0 1 1 1 1 0 0 0 : 1
VA3 VB3 1 1 0 0 1 1 0 0 1 : 1
VA2 VB2 1 1 0 1 0 1 0 1 0 : 1
VA1 VB1 1 1 0 0 0 0 0 0 0 : 1
VA0 VB0 0 1 0 0 0 0 0 0 0 : 1
VOLUME (dB) -43.5 -43.75 -44.0 -46.0 -48.0 -51.0 -54.0 -60.0 - : -
ADC mixer gain control
Two 8-bit values to program the channel 1 and 2 mixing, when the mixer mode is selected. Bits MA applies to channel 1 and bits MB to channel 2. The range is from +24 to -63.5 dB and - dB in steps of 0.5 dB. Table 45 ADC mixer gain settings MA7 MB7 0 0 0 : 0 0 0 1 : 1 1 1 1 1 MA6 MB6 0 0 0 : 0 0 0 1 : 0 0 0 0 0 MA5 MB5 1 1 1 : 0 0 0 1 : 0 0 0 0 0 MA4 MB4 1 0 0 : 0 0 0 1 : 0 0 0 0 0 MA3 MB3 0 1 1 : 0 0 0 1 : 0 0 0 0 0 MA2 MB2 0 1 1 : 0 0 0 1 : 1 0 0 0 0 MA1 MB1 0 1 1 : 1 0 0 1 : 0 1 1 0 0 MA0 MB0 0 1 0 : 0 1 0 1 : 0 1 0 1 0 MIXER GAIN (dB) +24.0 +23.5 +23.0 : +1.0 +0.5 0 -0.5 : -62.0 -62.5 -63.0 -63.5 -
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Philips Semiconductors
Product specification
Audio CODEC
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Ves Ilu(prot) Isc(DAC) PARAMETER supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage latch-up protection current short-circuit current of DAC note 2 note 3 Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. 4. DAC operation after short-circuiting cannot be warranted. 11 HANDLING - - note 1 CONDITIONS - - -65 -40 -1100 -250 MIN. 4
UDA1342TS
MAX. V 150 +125 +85 +1100 +250 200 450 325
UNIT C C C V V mA mA mA
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". 13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 90 UNIT K/W
thermal resistance from junction to ambient in free air
14 DC CHARACTERISTICS VDDD = VDDA(ADC) = VDDA(DAC) = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA(ADC) ADC analog supply voltage VDDA(DAC) DAC analog supply voltage VDDD digital supply voltage 2.7 2.7 2.7 3.0 3.0 3.0 3.6 3.6 3.6 V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
SYMBOL IDDA(ADC)
PARAMETER ADC analog supply current
CONDITIONS 1 ADC + 1 PGA enabled 2 ADCs + 2 PGAs enabled all ADCs + all PGAs power-down - - - - - - - -
MIN. 10 20
TYP. - - - - - - - -
MAX.
UNIT mA mA A mA A mA mA mA
200 6.0 250 9.0 4.5 5.5 - - - -
IDDA(DAC) IDDD
DAC analog supply current digital supply current
operating DAC power-down operating ADC power-down DAC power-down
Digital input pins (5 V tolerant TTL compatible) VIH VIL ILI Ci VOH VOL Vref Ro(Vref) VADCP VADCN Ri Ci Io(max) RL CL Notes 1. All supply connections must be made to the same power supply unit. 2. VDDA = VDDA(DAC) = VDDA(ADC). 3. When higher capacitive loads must be driven, a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. HIGH-level input voltage LOW-level input voltage input leakage current input capacitance IOH = -2 mA IOL = 2 mA with respect to VSSA(ADC); note 2 2.0 -0.5 - - 5.5 +0.8 1 10 - 0.4 V V A pF
Digital output pins HIGH-level output voltage LOW-level output voltage 0.85VDDD - - - V V
Reference voltage reference voltage output resistance on pin Vref positive reference voltage of the ADC negative reference voltage of the ADC input resistance input capacitance 0.45VDDA 0.5VDDA - - - - - (THD + N)/S < 0.1% note 3 - 3 - 5 0.55VDDA V - k
Analog-to-digital converter VDDA(ADC) - 0.0 10 24 - - - - - 50 V V k pF
Digital-to-analog converter maximum output current load resistance load capacitance 1.6 - - mA k pF
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
15 AC CHARACTERISTICS VDDD = VDDA(ADC) = VDDA(DAC) = 3.0 V; fi = 1 kHz at -1 dB; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - TYP. MAX. - - - - - - - - - - UNIT
Analog-to-digital converter Vi(rms) input voltage (RMS value) 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting Vi (THD + N)/S48 unbalance between channels normal mode; at -1 dB total harmonic distortion-plus-noise to 0 dB setting signal ratio at fs = 48 kHz 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting normal mode; at -60 dB; A-weighted 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting double differential mode at 0 dB gain at 0 dB gain; -60 dB input; A-weighted - - -93 -41 - - dB dB - - - - - - - - - -40 -37 -36 -35 -33 -31 -30 -28 -26 - - - - - - - - - dB dB dB dB dB dB dB dB dB 900 640 450 320 225 160 122.5 80 61.25 <0.1 mV mV mV mV mV mV mV mV mV dB
- - - - - - - - -
-90 -90 -90 -90 -89 -89 -88 -87 -85
- - - - - - - - -
dB dB dB dB dB dB dB dB dB
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
SYMBOL (THD + N)/S96
PARAMETER
CONDITIONS
MIN. - - - - - -
TYP. -84 -39 100 101 99 100 30
MAX. - - - - - - -
UNIT dB dB dB dB dB dB dB
total harmonic normal mode distortion-plus-noise to at 0 dB gain signal ratio at fs = 96 kHz at -60 dB; A-weighted signal-to-noise ratio at fs = 48 kHz signal-to-noise ratio at fs = 96 kHz channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) Vi = 0 V; A-weighted normal mode double differential mode Vi = 0 V; A-weighted; normal mode
S/N48
S/N96 cs PSRR
-
Digital-to-analog converter Vo(rms) Vo (THD+N)/S48 output voltage (RMS value) unbalance between channels at 0 dB total harmonic distortion-plus-noise to at -60 dB; A-weighted signal ratio at fs = 48 kHz total harmonic at 0 dB distortion-plus-noise to at -60 dB; A-weighted signal ratio at fs = 96 kHz signal-to-noise ratio at fs = 48 kHz signal-to-noise at fs = 96 kHz channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) code = 0; A-weighted code = 0; A-weighted at 0 dB (FS) digital input - - - - - - - - - - 0.9 <0.1 -90 -40 -83 -39 100 99 100 60 - - - - - - - - - - V dB dB dB dB dB dB dB dB dB
(THD+N)/S96
S/N48 S/N96 cs PSRR
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
16 TIMING VDDD = VDDA(ADC) = VDDA(DAC) = 2.7 to 3.6 V; Tamb = -20 to +85 C; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing; note 1 (see Fig.11) Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs tCWL tCWH system clock LOW time system clock HIGH time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial interface input/output data timing (see Fig.12) fBCK Tcy(BCK) tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-BCK) td(DATAO-WS) tr tf Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D bit clock frequency bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time data output to bit clock delay data output to word select delay - Tcy(s) = sample - frequency cycle time 30 30 - - 10 10 10 10 0 - - note 2 note 2 note 3 - - 500 250 250 190 190 190 190 - - - - - - - - - - - - - - - - - - - - - - 128fs
1 128Tcy(s)
35 23 17 17 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys
81 54 41 27 - - - -
250 170 130 90 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys
ns ns ns ns ns ns ns ns
Hz s ns ns ns ns ns ns ns ns ns ns ns
- - 20 20 - - - - - 30 30
L3-bus interface timing (see Figs 13 and 14) rise time fall time L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode 10 10 - - - - - - - ns/V ns/V ns ns ns ns ns ns ns
2000 Jul 31
32
Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
SYMBOL tstp(L3) tsu(L3)DA th(L3)DA tsu(L3)R th(L3)R ten(L3)R tdis(L3)R
PARAMETER L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA set-up time for read data L3DATA hold time for read data L3DATA enable time for read data L3DATA disable time for read data
CONDITIONS
MIN. 190 190 30 50 360 380 50 - - - - - - - - - -
TYP. - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns
I2C-bus interface timing (see Fig.15) fSCL tLOW tHIGH tr tf tHD;STA tSU;STA tSU;STO tBUF tSU;DAT tHD;DAT tSP Cb Notes 1. The typical value of the timing is specified at 48 kHz sampling frequency. 2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as small as possible. 3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 164fs cycle. 4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 5. After this period, the first clock pulse is generated. 6. To be suppressed by the input filter. SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL hold time START condition set-up time repeated START set-up time STOP condition bus free time between a STOP and START condition data set-up time data hold time pulse width of spikes capacitive load for each bus line note 6 note 4 note 4 note 5 0 1.3 0.6 400 - - 300 300 - - - - - - 50 400 kHz s s ns ns s s s s ns s ns pF
20 + 0.1Cb - 20 + 0.1Cb - 0.6 0.6 0.6 1.3 100 0 0 - - - - - - - - -
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Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.11 Timing of system clock.
handbook, full pagewidth
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
MGS756
Fig.12 Serial interface input data timing.
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34
Philips Semiconductors
Product specification
Audio CODEC
UDA1342TS
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.13 Timing of address mode.
handbook, full pagewidth
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK tsu(L3)DA th(L3)DA L3DATA write BIT 0 BIT 7
L3DATA read ten(L3)R tsu(L3)R tdis(L3)R
MGU015
th(L3)R
Fig.14 Timing of data transfer mode for write and read.
2000 Jul 31
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SDA t BUF t LOW tr tf t HD;STA t SP SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr
MBC611
Philips Semiconductors
Audio CODEC
P
Fig.15 Timing of the I2C-bus transfer. 36
UDA1342TS
Product specification
Philips Semiconductors
Product specification
Audio CODEC
17 APPLICATION INFORMATION
UDA1342TS
handbook, full pagewidth L1 +3 V BLM32A07 L2
BLM32A07 ground D A C12 100 F (16 V)
VDDD VDDA C13 100 F (16 V)
VDDA R16 1 R17 220 R15 1
C10 100 F (16 V) C23 100 nF (63 V)
C11 100 F (16 V) C24 100 nF (63 V)
C9 100 F (16 V) C22 100 nF (63 V)
VSSA(ADC) VDDA(ADC) VADCN system clock R13 47 DATAO BCK I2S-bus WS DATAI SYSCLK 1 12 3 5 7
VADCP VSSA(DAC) VDDA(DAC) 27 25
28 18 16 17 19 26
Vref C20 100 nF (63 V) C7 47 F (16 V)
VOUTL
C5 47 F (16 V)
R5 100 R11 10 k
C1 left input 1 right C3 left input 2 right 47 F (16 V) 47 F (16 V) C4 47 F (16 V) 47 F (16 V) C2
R1 0 R2 0 R3 0 R4 0
VINL1
left output
2
VINR1 4
UDA1342TS
24 VOUTR C6 R6 100 R12 10 k 47 F (16 V) right output
VINL2
6
VINR2 8
9 23
IPSEL QMUTE STATUS STATIC TEST1
L3MODE L3-bus L3CLOCK I2C-bus L3DATA
13 14 15 11 VSSD C21 100 nF (63 V) C8 100 F (16 V) R14 1 VDDD 10 VDDD
22 21 20
MGT021
Fig.16 Application diagram.
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Philips Semiconductors
Product specification
Audio CODEC
18 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1342TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
2000 Jul 31
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Philips Semiconductors
Product specification
Audio CODEC
19 SOLDERING 19.1 Introduction to soldering surface mount packages
UDA1342TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Audio CODEC
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1342TS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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40
Philips Semiconductors
Product specification
Audio CODEC
20 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
UDA1342TS
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 21 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 PURCHASE OF PHILIPS I2C COMPONENTS 22 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2000 Jul 31
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Philips Semiconductors
Product specification
Audio CODEC
NOTES
UDA1342TS
2000 Jul 31
42
Philips Semiconductors
Product specification
Audio CODEC
NOTES
UDA1342TS
2000 Jul 31
43
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/02/pp44
Date of release: 2000
Jul 31
Document order number:
9397 750 07241

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